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System-on-Chip Test Architectures: Volume

Nanometer Design for Testability
Artikelnummer: 978-0-12-373973-5
Einband: Fester Einband
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A guide to VLSI Testing and Design-for-Testability techniques that allows students, researchers, DFT practitioners, and VLSI designers to master System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs. It also includes practical problems at the end of each chapter for students.
A guide to VLSI Testing and Design-for-Testability techniques that allows students, researchers, DFT practitioners, and VLSI designers to master System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs. It also includes practical problems at the end of each chapter for students.
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VerlagElsevier
EinbandFester Einband
Erscheinungsjahr2008
Seitenangabe896 S.
AusgabekennzeichenEnglisch
MasseH23.5 cm x B19.1 cm x D4.2 cm 1'560 g
CoverlagMorgan Kaufmann Publishers In (Imprint/Brand)
ReiheSystems on Silicon
AutorWang, Laung-Terng / Stroud, Charles E. / Nur A. Touba

Alle Bände der Reihe "Systems on Silicon"

Über den Autor Laung-Terng Wang

Laung-Terng Wang, Ph.D., is founder, chairman, and chief executive officer of SynTest Technologies, CA. He received his EE Ph.D. degree from Stanford University. A Fellow of the IEEE, he holds 18 U.S. Patents and 12 European Patents, and has co-authored/co-edited two internationally used DFT textbooks- VLSI Test Principles and Architectures (2006) and System-on-Chip Test Architectures (2007).

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