Low Power Modem Design

A guidance to use novel algorithms (QPSK) and digital filters (FIR, IIR) with MATLAB, SIMULINK with VHDL and Xilinx FPGA
Artikelnummer: 978-3-659-75025-0
Einband: Kartonierter Einband (Kt)
Verfügbarkeit: Folgt in ca. 5 Arbeitstagen
CHF 92.00
decrease increase

This book is mainly concerned on use novel algorithms to reduce the power consumption used in modern digital modems e.g. QPSK. The designing and the simulation it will be in MATLAB. It will involve hardware implementation using VHDL and Xilinx FPGAs. In this project a novel low power modem will be designed for use in communication systems. For the designing it will use some of the modern radio communication technologies such as QPSK (OQPSK, BPSK etc) with the aim of designing and simulate a filter in MATLAB using Gaussian, Rayleigh and Rician channels. The simulation of QPSK and FIR filter will made in the SIMULINK of MATLAB. In this model will generate noise and how may bits it will transmitted and how many errors it will received. The final output of all is that in this model in a screen which called Error Rate Calculation. For the VHDL and Xilinx FPGAs will present an overview of the digital design and VHDL, the logic gates, the ASIC design and FPGAs. Finally for the VHDL and ASIC design, it is present schematic diagrams like full adders, parallel adders and multipliers from the Engineering Capture System (ECS).

This book is mainly concerned on use novel algorithms to reduce the power consumption used in modern digital modems e.g. QPSK. The designing and the simulation it will be in MATLAB. It will involve hardware implementation using VHDL and Xilinx FPGAs. In this project a novel low power modem will be designed for use in communication systems. For the designing it will use some of the modern radio communication technologies such as QPSK (OQPSK, BPSK etc) with the aim of designing and simulate a filter in MATLAB using Gaussian, Rayleigh and Rician channels. The simulation of QPSK and FIR filter will made in the SIMULINK of MATLAB. In this model will generate noise and how may bits it will transmitted and how many errors it will received. The final output of all is that in this model in a screen which called Error Rate Calculation. For the VHDL and Xilinx FPGAs will present an overview of the digital design and VHDL, the logic gates, the ASIC design and FPGAs. Finally for the VHDL and ASIC design, it is present schematic diagrams like full adders, parallel adders and multipliers from the Engineering Capture System (ECS).

Schreiben Sie Ihre eigene Bewertung
  • Nur registrierte Benutzer können Produkte bewerten
*
*
Schlecht
Sehr gut
*
*
*
*
VerlagLAP Lambert Academic Publishing
EinbandKartonierter Einband (Kt)
Erscheinungsjahr2015
Seitenangabe172 S.
AusgabekennzeichenEnglisch
MasseH22.0 cm x B15.0 cm x D1.1 cm 274 g
AutorGiannakopoulos, Georgios

Über den Autor Georgios Giannakopoulos

Georgios Giannakopoulos is Senior Lecturer in Modern History at City St George's, University of London

Weitere Titel von Georgios Giannakopoulos

Produktbewertungen
Nur registrierte Benutzer können Produkte bewerten